EDN

Synopsys Improves Memory Interface IP Integration

Synopsys, Inc. today announced the immediate availability of the DesignWare® DDR PHY compiler, supporting DDR2, DDR3, LPDDR and LPDDR2 SDRAMs. “As a leading fabless design integrator, GUC is committed ...
Electronic Design

Cadence and Denali Double-Team Advanced DDR-PHY Methodology

The combined resources of Cadence Design Systems and Denali Software have resulted in an advanced double-data-rate (DDR) PHY methodology based on Cadence’s Encounter digital IC design platform. The ...
Electronic Design

Test and Analysis GUI Targets DDR PHYs

This article appeared in Microwaves & RF and has been published here with permission. Check out our DAC 2023 coverage. At DAC 2023, OPENEDGES Technology will be in Booth 1354 demonstrating a beta ...
EDN

Synopsys Launches Full Range of Silicon-Proven DDR3 and DDR2 IP Solutions for SoC Designs

MOUNTAIN VIEW, Calif., Aug. 13 /PRNewswire-FirstCall/ — Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing ...
Design-Reuse

Denali DDR PHY for TSMC

LPDDR4/3, DDR4/3/3L, up to 4266Mbps The latest Denali high-speed DDR PHY IP is comprised of architectural improvements to its highly successful pre ...