EDN27d
DRAM basics and its quest for thermal stability by optimizing peripheral transistors
In the longer term, more disruptive solutions may be envisioned that break the traditional ‘2D’ DRAM chip architecture. One option is to fabricate the DRAM periphery on a separate wafer, and bond it ...
EDN25d
A new platform for thermally stable DRAM peripheral transistors
However, an improved technology for the periphery became necessary to keep pace with the performance enhancement enabled by subsequent generations of DRAM memory. The most obvious candidate was moving ...
Design-Reuse7d
A Methodology for Performance Analysis of Network-on-Chip Architectures for Video SoC
The majority of traffic flows from the different processing engines (henceforth called Masters or Initiators) converge into the DRAM memory. In other words, the system operates as shared memory ...
Hosted on MSN22d
Sandisk's revolutionary new memory promises DRAM-like performance, 4X capacity at half the price
The company says its scalable memory architecture will break through the ... will achieve over 50% cost savings per bit compared to DRAM, with a significantly steeper decline in $/GB, making ...
Design-Reuse7d
DRAM Controllers for System Designers
The block is far more than just an interface. In advanced system designs, the DRAM controller must mediate between the complex and unpredictable patterns of memory requests dictated by the SoC ...