Semiconductor Engineering

Understanding and Mitigating Column-Based Read Disturbance in DRAM Chips (ETH Zurich, CISPA)

Understanding Column-based Read Disturbance in Real DRAM Chips and Implications for Future Systems” was published by ...
Semiconductor Engineering

In-DRAM TRNG Using Simultaneous Multiple-Row Activation (ETH Zurich, CISPA)

DRAM True Random Number Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Real DRAM Chips” was ...
Ars Technica

There’s a new way to flip bits in DRAM, and it works against the latest defenses

In 2015, researchers reported a surprising discovery that stoked industry-wide security concerns—an attack called RowHammer that could corrupt, modify, or steal sensitive data when a simple user-level ...
EDN

Rambus: Micro-Threaded Row and Column Operations in a DRAM Core

The technique of micro-threading may be applied to the core of a DRAM to reduce the row and column access granularity. This results in a significant performance benefit for those applications that ...
EDN

Speed with flexible design critical to embedded DRAM for SoCs

Steven Tomashot, Senior Technical Staff Member, IBM Microelectronics Division, Essex Junction, Vermont, Subramanian S. Iyer, Manager, System Scale Integration, IBM Microelectronics Division, Hopewell ...