Semiconductor Engineering

Double Duty Logic Block Architecture Enabling Concurrent LUT and Adder Chain Usage (Nanyang Technological Univ. et al)

FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage” was published by researchers at Nanyang Technological ...
EDN

How to design an FPGA architecture tailored for efficiency and performance

Until relatively recently, the majority of FPGA architectures were developed using 4-input lookup tables (LUTs), where each LUT is constructed from SRAM bits storing digital (0 or 1) information. Also ...
Elektor Magazine

Mastering FPGA Chip Design with Kevin Hubbard, Elektor Engineering Insights #56

Learn real-world strategies about FPGA Chip Design, Join Elektor Engineering Insights on Sept 24 at 16:00 CEST with Kevin ...
Tech Xplore on MSN

Cracking a long-standing weakness in a classic algorithm for programming reconfigurable chips

Researchers from EPFL, AMD, and the University of Novi Sad have uncovered a long-standing inefficiency in the algorithm that ...
EDN

Hybrid architecture embeds Xilinx FPGA core into IBM ASICs

SAN MATEO, Calif. — Undeterred by earlier false starts for programmable ASICs, IBM Corp. and Xilinx Inc. are embarking on a plan to jointly create an architecture that melds an FPGA core with a ...
Semiconductor Engineering

Manycore-FPGA Architecture Employing Novel Duet Adapters To Integrate eFPGAs in a Scalable, Non-Intrusive, Cache-Coherent Manner (Princeton)

A technical paper titled “Duet: Creating Harmony between Processors and Embedded FPGAs” was written by researchers at Princeton University. “The demise of Moore’s Law has led to the rise of hardware ...
The Next Platform

Intel FPGA Architecture Focuses on Deep Learning Inference

There has been much written about the potential for FPGAs to take a leadership role in accelerating deep learning but in practice, the hurdles of getting from concept to high performance hardware ...
The Next Platform

Xilinx Unveils xDNN FPGA Architecture for AI Inference

FPGAs might not have carved out a niche in the deep learning training space the way some might have expected but the low power, high frequency needs of AI inference fit the curve of reprogrammable ...
Electronic Design

Modular FPGA Architecture Spawns Multiple Silicon Optimizations

Though FPGA designers have tried to keep FPGAs as generic as possible, Xilinx feels it's time to craft FPGAs that are more in tune to specific market segments. To do this, its next-generation Virtex ...
Electronic Design

Architecture Supports Multiple Domain-Specific FPGA Platforms

Defined as revolutionary, the Application Specific Modular Block (ASMBL) architecture promises rapid, cost-effective deployment of multiple domain-specific FPGA platforms with a blend of features.
Design-Reuse

How to utilize advanced FPGA features without getting locked into an architecture

A vendor-independent design approach that allows design development independent of the target FPGA architecture can pay big dividends. Programmable logic in today's FPGAs now provides more than just ...
VentureBeat

FPGA chips are coming on fast in the race to accelerate AI

AI is hungry, hyperscale AI ravenous. Both can devour processing, electricity, algorithms, and programming schedules. As AI models rapidly get larger and more complex (an estimated 10x a year), a ...